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EPLD and EPROM Programming Lab


Objectives:

1. To improve the students understanding and hardware programming skills with Erasable Programmable Logic Device (EPLD) and Electrically Programmable Read Only Memory (EPROM)

2. To review basic logic hardware devices

3. To review basic logic analyzer functions and to introduce advanced logic operations


Materials:
1.
EPROM (2716)
2. EPLD (EP600)
3. Encoder
4.
Logic Analyzer


Procedure:

1. Write a program, using ORCAD to implement the circuits shown in Figure 1.

2. Program an Erasable Programmable Logic Device (EPLD) to implement Figure 1.

a) Test the EPLD to verify proper operation.

b) Use the logic analyzer to verify the operation of the counter.


3. Obtain a pre programmed Electrically Programmable Read-Only Memory (EPROM).

a) Determine experimentally the data stored in the EPROM. The student should be able to associate each bit of the stored data with an output pin.


4. Connect the EPROM to the EPLD as shown in Figure 2.

a) Predict the EPLD OUTPUTS.

b) Using the logic analyzer observe the EPLD outputs and compare to predicted values.

c) Save logic analyzer waveforms on a disk.


5. Required written material to be turned in. All students will turn in the following:

- The complete LST file from ORCAD.

- A schematic showing how the EPLD was tested.

- Truth tables, state tables, or what was needed in the testing scheme. Also the results of the tests.

- PROM table showing the addresses and data.

- Schematic showing EPROM and EPLD connected together.

- EPLD output predictions.

- Disk containing logic analyzer waveforms of EPLD outputs.


Procedure & Data:

For the given experiment a logic design was examined using an EPLD and EPROM. The objective for the laboratory experiment was to design a logic network using an EPLD and verify the operation of the chip. Also an EPROM was provided with unknown data programmed into the chip where by we were to predict and extract the programmed data.


Figure 1: ELPD Configuration




First a program was developed for a 4 bit binary counter, 2 to 4 decoder, and 4 to I multiplexer. These logic equations were developed and written into ORCAD (see notes, page 1). Next the program was burned into an EPLD and tested for efforts. Each device was tested by inputting a known logic signal into the EPLD and with the use of a logic probe the output was predicted and confirmed. Finally the 4 bit binary counter was tested by connecting a logic analyzer to the chip and verifying its ability to count.

Next a EPROM was obtained having stored within it memory unknown data. Using a dip switch to input a four bit binary address into the EPROM and with the use of a logic probe each output pin was measured there by extracting the data.

Figure 2: ELPD & EPROM Configuration


Once the data was extracted from the EPROM predictions were developed for the behavior characteristics, of the EPLD when connected as shown in Figure 2. (See predictions on page 3 of notes) The EPLD, EPROM was connected together and displayed on the logic analyzer for comparison to the predicted data. The output wave forms of the EPLD were generated and printed (see Figure 3).




Figure 3: Logic Analyzer Output for EPLD



Conclusion & Discoveries:

The predicted data in which the method of signal tracing was used to develop an understanding of the circuit's characteristics matched the output data obtained experimentally.

By converting the ORCAD program for each device stored in the EPLD to a short hand method where by the equations were condensed allowed for shorter yet powerful logic statements.

In closing the review of programming EPLD's and the new method of condensing logic equations proved very helpful with the use of ORCAD. Also by testing each programmed device for correct operation allowed for greater confidence in generating the proper expected output for the device. With the EPROM, by examining the data stored within the device and retrieving the program proved very helpful in the method of digital logic analysis.


Lab Notes
Lab Notes Page 1
Lab Notes Page 2
Lab Notes Page 3

Lab Data
Signal Assignment
PLD Compiler Source File
OrCAD PLD EP600 Output File


Electrical Engineering lab key words: EPLD, EPROM Programming, ROM, Microcontrollers, Erasable Programmable Logic Device, Electrically Programmable Read Only Memory, Configuration, operations, timing, logic hardware, on-chip, peripherals, microcontroller trainer, logic analyzer, assembly language, predicted values, testing, programming data, I/O ports, parallel ports, strobe, modes of operation, logic circuits, up-down counter, latches, timing loop, data memory, and output waveforms.

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