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JFET Characteristics and Biasing Lab
N-Channel junction field effect transistor characteristics laboratory experiment using the 2N5457 through 2N5459 series general purpose JFET.
The experiment will expand on and verify theoretical concepts presented in the lecture course Analog and Semiconductor Devices through the
use of bench top device measurements, hand calculations, and PSpice simulations.
Procedure:
1. Design and use a test circuit incorporating bench instruments to measure the output (drain) characteristics
of a 2N5458 JFET when VGS = 0; e.g. ID vs. VDS for VDS = 0 to 15V. Plot the results on graph paper.
9. Construct the circuits shown in Figures 1, 2 and 3 using values calculated in step 8. For each circuit:
a. Measure ID and VDS (transistor with larger IDSS)
b. Change FETs and measure ID and VDS
*Included to establish Zin in a practical amplifier; not required for this experiment.
10. Perform PSPICE analysis on the circuits shown in figures 1, 2, and 3. Compare the results to the measured
values obtained in step 9a.
Note: VTO = VP , BETA = IDSS / VP2
Conclusion & Discoveries:
By using bench test measurements, a more accurate analyses can be numerically determined for the 2N5458 JFET.
Electrical Engineering lab key words: JFET, junction field effects transistor, JFET characteristics, biasing, q point, n-channel, FET, gate, source,
drain, IDSS, VGS, 2 port model, frequency response, transfer function, Pspice simulation, self bias, fixed bias, combinational bias, VDD,
differential amplifier stage.
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