|
|
Related experiment notes and graphics:
JFET lab bench calculations for Figure 1.1 and Figure 1.2. Input resistance stage, VDD and drain current,
gate voltage, and source resistance computations. This graphic image maybe used for publications, web sites,
or any print or electronic media with the express intent that the image is not altered and the author
properly sited. You agree to these conditions upon any use of this image.
|