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JFET Small Signal Amplifier Lab
Objectives:
1. To become familiar with the characteristics of a JFET small signal amplifier.
2. To reinforce design principles for biasing a JFET.
Procedures:
1. On a sheet of graph paper, draw the transfer curves corresponding to the maximum and minimum values of IDSS and
VGS(off) from the 2N5458 specifications. On the same set of axes, draw the transfer curve for the JFET with the higher
value Of IDSS which was used in the previous experiment.
2. Design a combinational bias circuit using the following criteria:
a. Using the measured transfer curve, select a quiescent value of ID that will maximize the peak to peak range of iD without distortion.
b. Select values of VG and Rs that will establish a Q-point at the same relative position on the maximum and minimum transfer curves.
c. Set VDD = 20V. Set VDS = to 1/2 (VDD - IDRS), at the Q-point. Using KVL, find RD.
d. Bypass Rs with a 100μF capacitor; couple the input and output signals through 4.7μF capacitors.
e. Let Ri(stage) ≈ 100kΩ , solve for R1 and R2. Assume RL ≈ ∞ (i.e. 10MΩ input of 10X scope probe).
3. Draw the DC and AC load lines on the output characteristics for the JFET used.
7. Measure Av for 10Hz ≤ f ≤ 10MHz. Plot gain in dB vs. frequency on semilog paper.
8. Replace the JFET with a second JFET, determine the Q-point and then re-measure Av, and vgs(max)
9. Using predetermined values for BETA, VTO, and LAMBDA, simulate the first JFET circuit on
PSPICE and compute ri(stage) , ro(stage) , Av , vgs(max) ,
and the frequency response. Compare PSPICE, hand calculations, and experimental measurements.
Procedure & Data:
1. In the given experiment the characteristics of a FET Small Signal Amplifier and biasing techniques were
examined. First a graphical plot was developed to determine the operating range of the device. Maximum and
minimum transfer curves were plotted using data provided by the manufacture and the transfer curve used in
the previous experiment (Tran. 1) was transposed on the same graph (figure 1). By inspection, Tran. 1 set
close to the operating range of the minimum curve yet provided a suitable device for the experiment. Once
plotted a VGG liner load line Q-point of +1V was chosen with a slope to accurately depict equal
distance above and below on the transfer curve. In choosing the above parameters VG= 1V and when
plotted vs. ID, the intersection of the Q-point found ID = 1.5mA.
Secondly, a combination bias circuit was designed with specific parameters specified by the laboratory experiment
(figure 1.1). Using the above figures of ID and VG and incorporating them into the design
circuit a VDD was set equal to 20V and VDS set equal to 0.5(VDD - ID RS).
By using KVL around the loop, RD was calculated (table 1).
In the next sequence of the laboratory experiment the design circuit was reconstructed with the following additions.
Rs was now bypassed using a 100 μF capacitor in parallel and the input and output signals were coupled using 4.7 μF
capacitors (figure 1.2). Once the additions were added to the design circuit values for the biasing resistors R1
and R2 were calculated Ri(stage) ≈ 100kΩ , RL ≈ ∞. By assuming
R2 = 10k Ω , R1 was easily determined using the following equation (E.1).
For the next section of the experiment graphical analysis was incorporated to determine Vgs and the gain Av of the
circuit. By examining minimum transfer curve in figure I and plotting an equal swing around the Q-point both horizontally
and vertically, Vgs(max) was located and recorded (table 1). As for the gain Av, the ratio of the maximum swing and minimum
swing voltages on the transfer curve were calculated using the following equation (E.2) and recorded (table 1).
Av = ΔVO / ΔVIN (E.2)
Table 1: Calculated & Assumed Values for Combination bias Circuit
Once graphical analysis was completed a small signal mid band AC equivalent circuit model (S.S.M.B.E.C.) was constructed
to better understand the design circuit (figure 1.3). By using the model for the circuit three relationships needed to be
calculated and recorded (table 2). The input resistance (Ri(stage)) (E.3), output resistance (Ro(stage)) (E.4), and the gain
(Av) (E.5), was calculated using the following equations.
After all calculations and graphical analysis were completed, the design circuit (figure 1.2) was constructed in the
laboratory with an input AC source at a frequency of 10kHz and measurements were taken. The Q point, gain (Av), Ri(stage),
Vgs, and Vo were measured and compared to the previous data obtained (table 3). To better understand the characteristics of
the gain (Av) the input frequency was sweep from 10Hz to 10MHz by a factor of 10 (table 4). For graphical proposes the measured
was converted to dB by taking the log of the gain (Av) and multiplying it by 20. Then a log scale plot using semilog paper
was constructed for frequency vs. dB (figure 2).
Table 4: Table 4: Frequency vs. Gain (Av) & AVdB for S.S.M.B.E.C.
A second JFET device was introduced into the design circuit as a way to gain a better understanding of the devices
characteristics by measuring the Q point, gain (Av), and Vgs(max) for the new device. These values were then compared
to the first device in the following table (table 5).
Table 5: JFET 1 vs. JFET 2 Measured Values in the Operational Range
For the last section of the laboratory experiment Pspice simulations for the original NET (JFET 1) were ran to confirm
the measured and calculated results. First the circuit was simulated using values previously derived in past laboratory
experiments for VTO, BETA, and LAMBDA. Output operating point information was constructed and values compared measured
and calculated results (table 6). Plots were constructed for the gain (Av) (figure 3), Q point verification (figure 4),
and current through the source resistor (figure 5). One simulated comparison was the confirmation of the same current
IRD = IRS do to the fact that no current flows back through the device at the gate (figure 4 & 5). Another comparison
was made and plotted to examine the characteristics of the relationship between Rs and Cs as frequency changes. Therefore,
a graphical representation of the effect frequency has on the bypassed Rs is noted (figure 6).
Table 6: Calculated, Measured, & Pspice Simulations Comparison for JFET 1
Conclusion & Discoveries:
Controlling the input resistance by varying the value of RG allows one to design a device to the needed gain (Av)
required to the design project.
The use of creating a small signal model provides one to more easily determine the characteristics by inspection. This model
allows ease of analysis and provides a greater understanding of the behavior of JFETs.
By examining the source resistance and the bypass source capacitor a better understanding of the characteristics was
discovered over a large frequency range.
In closing, by examining the small signal amplifier and the S.S.M.B.E.C. a better understanding of the JFET's characteristics
and applications was learned. By looking at the operating range and the ability to control the input and output impedance's
with the load and RG a device or several devices can be designed to produce the desired gain (Av).
Electrical Engineering lab key words: FET Biasing, FET Small Signal Amplifier, Q-Point, 2N5458,
Analog Devices and Circuits, quiescent point, IDSS, parallel circuit, load, JFET Small Signal
Amplifier Lab, Design Principles for JFET Biasing, 2N5457, 2N5459, FET Transfer Curve,
q point, Analog Devices.
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