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III. Phase-Locked-Loop Component Subsections

3.1 DC Current Bias

3.1.1 Widlar Current Source

Current Bias is accomplished by a widlar current source, as shown in Figure 3.1.1. The Widlar current source allows for direct coupling without loading connected stages. The emitter resistors provide stability, and allow for variable current source.

3.1.2 Calculation of Current Values

The current values were calculated by doing loop equations that include the emitter resistors and the voltage drops from the base to the emitter, Vbe, of each transistor. The following derivation is for the amplifier current, ICQ39, as shown in Figure 3.1.2.

 Loop equation: IcQ38(R4 + VbeQ38) = IcQ39(R15 + VbeQ39) Where: VbeQx = (ln(IcQx) - ln(IsQx))ηVt ηVt = 25.5mV R4 = 200Ω R15 = 205Ω IcQ38 = 820μA Then: IcQ39 = 802μA

3.1.3 DC Current Bias Simulation

In order to simulate the CA3046 transistor array, characteristic measurements were taken because the version of PSPICE available to use did not include a model for the CA3046 in its libraries. We had to modify the model of the Q2N2222 with values that we measured from the CA3046 transistor array. We were not able to make all the measurements for the characteristics that are included in the model for the Q2N2222, so we left these characteristics so alone. The result of including the unmeasured characteristics caused the beta of the transistors to drop form above 100 to below 20. We had to change the characteristics that we did not measure to standard values in order to get the beta above 100. The characteristic that dropped beta the most was Ise. The following is the model that we used for simulating the CA3046 transistor array.

 .model CA3046-X NPN( Is=19.3f Xti=3 Eg=1.11 Vaf=204 Bf=102 Nf=1.147 Ne=1.307 Ise=0 Ikf=1000000Meg Xtb=0 Br=1 Nc=2 Isc=0 Ikr=1000000Meg Rc=0 Cjc=1.3p Mjc=.5 Vjc=.75 Fc=.5 Cje=1.02p Mje=.33 Vje=.75 Tr=0 Tf=243p Itf=0 Vtf=1000000Meg Xtf=0 Rb=0 Cjs=6.26p Vjs=.75 Mjs=.5 Re=0) * CA3046 NPN model *\$

3.1.4 Measured Results

The calculated, simulated, and measured values for the DC current biases are shown in Table 3.1.1. The calculated values shown in the table assume ideal characteristics, which accounts for their differences from simulated and measured values. Differences in simulated and measured can be attributed to the fact that the CA3046 transistors used in the actual circuit do not exactly match the simulation characteristics we included in the PSPICE model for the CA3046.

Table 3.1.1 Values for DC bias currents. Electrical Engineering lab key words: Phase Lock Loop, Direct Current, DC Bias, DC Components, Widlar, Current Sourse, transistor characteristics and influence, coefficients, levels, electrical, BJT, PLL, amplifier biasing, cathode and fixed, current flow, CA3046, Q2N2222, Pspice Simulation.

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