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Phase Locked Loop Project Overview

I. Abstract

An electronics engineering technology term project involving the analysis, construction and simulation of the National Semiconductor LM565 Phase-Locked-Loop. Detailed analysis of subsections and final construction of an emulated LM565 PLL using transistor arrays and discrete devices are discussed.

II. Phase-Locked-Loop Project Overview

2.1 Introduction, Goals, and Typical Applications

For this project, an analog integrated circuit design project involving the reverse engineering of a phase-locked-loop (PLL) was undertaken. The LM565 PLL manufactured by National Semiconductor was chosen because of its general properties and accessibility to the circuit's design. The LM565 was carefully dissected into four components and each section was assigned to a member in the four-member team.

The overall project goals for the term were to emulate the National Semiconductor LM565 Phase-Locked-Loop using CA3046 / CA3096 general transistor arrays, and discrete devices. Also to match or exceed the manufactures specifications for the LM565.

During the 10week course each member of the design team would be responsible for analyzing, construction and simulating all the response characteristics of their sections. The team would also interconnect each section of the device and construct a working PLL emulating the characteristics of the National Semiconductors LM565 PLL. A PLL is a device used primarily in communication systems for modulating, demodulation signals and performing frequency generation. Both analog and digital PLL are available from manufactures each being specific to the function they perform. However in general PLL are commonly composed of only a few simplified elements. At the input to the PLL is a phase detector, followed by a low pass filter, an amplifier, and a voltage-controlled oscillator (VCO) (see figure 2.1.1).

Figure 2.1.1: Phase-Locked-Loop Block Diagram

2.2 Theory of Operation

In general, a PLL is a closed loop device that produces an output signal based on the difference between the input signal and the VCO's free running frequency. For example, if the VCO frequency is matched to the input signals frequency then the two signals are considered "locked-on" and an output signal is generated relative to the difference between the VCO's free running frequency and the "locked-on" frequency. Hence when the input signal changes relative to the VCO's frequency, a change in the output signal occurs. However this change does not happen instantaneously. There is a time delay from the input signal change to the VCO locking onto the input signal. Therefor the input signal cannot change any faster then the VCO can "lock-on" to the signal.

Also associated with a PLL is the range of frequencies the VCO can track over. Not all frequencies can be locked onto with a PLL so the nature of the input signal must be known prior to choosing a device. The "lock range" of the PLL is the range around the VCO's free running frequency that can be generated. For the LM565 the typical range is 7kHz, centered on 12kHz. However not all frequencies generated by the VCO can be locked onto. For this a "capture range" is defined as the range of frequencies the PLL can maintain lock-on.

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