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Transistor Array Characterization for PLL - CA3046 & CA3096

IV. CA3046 & CA3096 Transistor Array Characterization

4.1 Transistor Characterization

For the emulation of the LM-565 Phase Lock Loop, discrete BJTs, resistors and capacitors were used. For current mirror operation and analysis matched BJTs are required to allow the associated current mirror assumptions to be made. This necessitated the use of the CA3046 and the CA3096.

The CA3046 is an integrated circuit (IC) that contains one matched NPN emitter coupled pair BJTs and three individual NPN matched BJTs. The CA3096 is also an IC but it contains two matched PNP BJTs and three matched NPN BJTs. The discrete implementation contained only the CA3046 and CA3096 ICs for all BJT transistors.

To maximize the PSPICE analysis and circuit implementation, the discrete transistors must be characterized. Device characteristic parameters can be obtained using a curve tracer around the average operating range of the overall circuit (100μA). Once these values are obtained curve fitting methods are used to solve for Beta, Eta, early voltage (VA), and the leakage current (IS). The resultant values are then used in the PSPICE analysis and hand calculation. The resultant values and specification sheet values are contained in Table 4.1.1.

Table 4.1.1 NPN and PNP measured and specification sheet data at 100μA.

Electrical Engineering lab key words: BJT, bi-polar junction transistor array, transistor characterization, phased locked loop, PLL, CA3046, CA3096, NPN, PNP, IC, matched pairs, manufactures, National Semiconductor, Maxim IC, applications, low-levels, common substrate, thermal properties, differential, general purpose, low noise and wide current range, low power, VHF, package, Pspice, curve fit, curve tracer, specifications sheet, data sheet, spec sheet, leakage current, early voltage.

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