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Phase Locked Loop - Voltage Controlled Current Source (VCCS)
3.4 The Voltage Controlled Current Source
The Voltage Controlled Current Source is an integral part of the LM-565 Phase Lock Loop. The purpose of this current source is to provide charging
and discharging of the timing capacitor, Ctime. This charging and discharging of the capacitor produce a triangle waveform, which is then feed onto
the Schmitt, trigger circuit section for voltage level triggering. The Voltage Controlled Current Source can be separated into two main subsections,
the upper-half-circuit subsection and the lower-half-circuit subsection which can be seen in Figure 3.4.1.
The division between the two subsections can be made by noting that the current entering the Voltage Controlled Current Source from the source VCC is
the same as the current leaving from sum of both IE15 and IE16. Therefore, the logical division is at this point considered the lower-half-circuit and
the upper-half-circuit subsection shown in Figure 3.4.2 results.
To find the voltage at VX an equation around the loop containing Q12, Q13
and VCOcontrol can be written using KVL which results in:
Figure 3.4.4 Lower-Half-Circuit showing Upper-Half Circuit Simplification
With the switch S1 open, also called the charging phase, zero current will flow through D17, Q19, Q20, and Q21. This effectively reduces the circuit to include only ICS, D18,
and Ctime, which is shown in Figure 3.4.5. The capacitor Ctime voltage will increase linearly as a function of the capacitor current ICtime.
Since no other path exists for the current ICS to flow through except into Ctime, then ICS equals ICtime. The slope of the voltage across the capacitor is
determined by the equation:
Slope = ICS / Ctime
The variation in VCOCONTROL produced by the phase difference on the input to the Phase Lock Loop causes ICS to vary, causing the slope of the voltage across the
timing capacitor to vary. As VCOCONTROL decreases, ICS increases, and the slope increases. This capacitor charging voltage is the first half of the triangle wave
that is the input to the Schmitt Trigger.
When S1 is closed by the Schmitt Trigger, the capacitor discharge phase is entered shown in Figure 3.4.6. The closing of S1 allows current to flow through the Emitter
Degenerative Resistive Wilson current source made up of Q19, Q20, Q21, R16 and R17. The closing of S1 and the current flowing through the Wilson current source "pulls" the
anode of D17 toward negative VCC minus three diode drops and the voltage across R17 or approximately negative three point nine volts, thereby reverse biasing D18.
With no current flowing through D18 due to the reverse biased state, all of ICS must flow through D17. Assuming base currents are small and thereby negligible, all of ICS
flows through Q20. By operation of a current mirror, the current through Q20 is matched by the current through Q19 and Q21. Since no current can flow through D18 all of the
current must come from the capacitor current ICtime, therefore ICS equals ICtime.
The slope of the voltage across the timing capacitor is also determined by the slope equation given above. With S1 switching on and off symmetrically a triangle waveform is
generated across the timing capacitor. By varying VCOCONTROL, the magnitude of the slope of the triangle waveform varies. As VCOCONTROL increases, the slope
decreases and ICS decreases.
The control and predictability of ICS is accomplished using some advanced techniques in semiconductor construction. In the upper-half-circuit, a triple collector PNP BJT is used
for current matching. In most BJTs the collector contact is a solid ring around the emitter contact. When the collector contact is equally divided into two, three or four contacts,
the current from each section is exactly matched which is essential for the correct operation of the upper-half-circuit. The topology and schematic symbol is shown in Figure 3.4.7.
Figure 3.4.7 Triple Collector PNP BJT Topology and Schematic Symbol
The upper-half-circuit shown in Figure 3.4.8 is the Signetics schematic diagram. A simplified form is shown in Figure 3.4.9 where the triple collector PNP BJT is shown as three
separate BJTs. ICS is separated into exactly quarters by using the triple collector BJT. Thus, the current through Q15 exactly matches the current through Q16 and the sum of the
two currents equals ICS.
Figure 3.4.10 shows the PSPICE simulation of the Voltage Controlled Current Source. The triangle waveform is the voltage across the capacitor which is provided to the Schmitt
Trigger. The second waveform is the voltage across the diode connected transistor Q18 showing the forward and reverse bias conditions. The positive voltage is the capacitor
charging phase and the negative voltage is the capacitor discharge phase.
Figure 3.4.10 PSPICE Simulation of the Voltage Controlled Current Source
Electrical Engineering lab key words: VCCS, voltage controlled current source, PLL, phased locked loop, quality,
clean current, load, resistor, resistance, variable, buffer circuit, clipping, amplifier, amplification, max load,
temperature, voltmeter, ammeter, gain and depend sources, Schmitt trigger, timing capacitor, KVL, capacitor
discharge, BJT, ICS, VCO, relationship, node, control signal, diode, emitter, collector, Wilson current source,
anode, PNP, NPN, IC, BJT matched pairs, Pspice. |
