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Synthesis of a Pattern Detector Lab


Objective:

1. To apply engineering design principals in designing a sequential circuit given a written description

2. To simulate and optimize a sequential circuit using computer simulation tools such as ORCAD

3. To program a Programmable Logic Device (PLD) to perform the sequential circuit functions

4. To generate an engineering test sequence to tests and verify the PLD design




Problem Statement:

Design, simulate, construct, and test a Mealy circuit which has one input (labeled X) and three outputs (labeled Z1, Z2, and Z3).

a) Z1 will produce a logic 1 output in response to the input sequence 1001.
b) Z2 will produce a logic 1 output in response to the input sequence 1010.
c) Z3 will produce a logic 1 output in response to the input sequence 0110.

The input sequences may overlap, that is, the search is not restarted when any target input sequence occurs.





Procedure:

1. List a sample of input and output signals and draw the Algorithmic State Machine (ASM) chart.

2. Engineer the circuit design. Implement using D Flip Flops.

3. Create and evaluate computer simulations using ORCAD or similar digital logic computer simulation software. The input patter should test every path on the state graph.

4. Implement the circuit using an EP600. Verify the operation using the sequence generator design in Experiment 1. Use a logic analyzer and waveform generator to verify the engineered circuits correct operation.

5. For the laboratory report turn in the following products. The circuit design, computer simulation waveforms, schematics, list files, and logic analyzer tests demonstrating the operation of the sequential circuit.



Conclusions and Discoveries:

For the first part of the experiment an algorithmic state machine chart (ASM) was created to graphically represent the input / output and various states of the sequential circuit. The Mealy circuit was found to have the following specifications. The circuit will have one input, three outputs, and produce an output response when one of three specific bit sequences was detected which would producing a specific output based on the detected sequence.

A block diagram of inputs and outputs was drawn followed by implementing the design in a state diagram. From the state diagram we reduced the necessary states with those having repetitive states. Then from the reduced state table an algorithmic state machine chart was developed listing all possible data paths and output combinations. Once the algorithmic state machine chart was developed and pathways optimized, state assignments were considered. Upon development of the state assignments, next state equations were written and reduced.


Implementing the use of D flip flops throughout the design and several basic logic gates, the circuit equations derived above were programmed into an EP600 programmable logic device (PLD).


Lab Notes
Lab Notes Page 1
Lab Notes Page 2
Lab Notes Page 3
Lab Notes Page 4

Figures and Graphics
Graph 1: Pattern Detector Layout
Graph 2: Source Expressions
Graph 3: Signal Assignment
Graph 4: Output Memory File


Electrical Engineering lab key words: pattern detector, logic Analyzer, digital circuit and systems, experiments, hand calculations, computer simulations, theory, hardware components and instrumentation, Karnaugh Maps, truth tables, Boolean expression, ORCAD, PLD design, ASM Chart, state assignment, EPROM, K-Maps, logic gates, logic analysis, clocking, digital fundamentals, decimal, binary, hexadecimal, conversions, number systems, arithmetic operations, BCD code, parity bit, LSB, least significant bit, Boolean algebra, simplification theorems, SOP or POS, decoders and multiplexers, flip-flops, sequential circuits, PLAs, ROMs, LSI devices.

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